Secondary radar reception system

ABSTRACT

A secondary radar reception system having a primary radar, a secondary radar receiver receiving a response wave transmitted from a secondary radar in response to a radar signal from the primary radar, and a synchronization control circuit interposed between the primary radar and the secondary radar receiver, the secondary radar receiver having an identification circuit which has a multiple delay circuit consisting of at least two separate multiple delay circuits with at least one multiplier circuit being interposed therebetween, a first input terminal of the multiplier circuit being supplied with the output of a first separate multiple delay circuit, a second input terminal being supplied with the response wave from the secondary radar and an output terminal being connected to the input side of a second separate multiple delay circuit.

iiited States Patent [151 3,697,991

()hyama et al. 5] Oct. 10, 1972 1541 SECONDARY RADAR RECEPTION 3,307,1852/1967 Mefford ..343/17.1 R

SYSTEM Primary Examiner-T. H. Tubbesing [72] Inventors: Takashl OhyamaTokyo; Akin Attorney-Hill, Sherman, Meroni, Gross & Simpson Kawashige,Yokohama; Takeo Miyashita, Saitama, all of Japan 57] ABSTRACT [73]Asslgnee: xabushlklkfuha Tokyo Selzosho A secondary radar receptionsystem having a primary (Tokyo Ke'kl Selzosho Ltd), radar, a secondaryradar receiver receiving a response Tokyo Japan wave transmitted from asecondary radar in response [22] Fil d; M h 9, 1970 to a radar signalfrom the primary radar, and a synchronization control circuit interposedbetween the [21] Appl. No.: 17,739 primary radar and the secondary radarreceiver, the

secondary radar receiver having an identification cir- [30] ForeignApplication Priority Data cuit which has a multiple delay circuitconsisting of at least two separate multiple delay circuits with atleast March 11, 1969 Japan ..44/ 18199 one lti li r circuit beinginterposed therebetween, March 11, 1969 Japan ..44/29552 a fi input t il f the m ltiplier circuit being supplied with the output of a firstseparate multiple [52] 11.8. C1. ..343/6.5 LC, 343/ 17.1 R delaycircuit, a second input terminal being supplied [51] Int. Cl ..G01s 9/56with the response wave from the secondary radar and [58] Field of Search..343/6.5 R, 6.5 LC, 17.1 R an output terminal being connected to theinput side of a second separate multiple delay circuit. 56 R f C't d 1 eemnces l e 6 Claims, 92 Drawing Figures UNITED STATES PATENTS 3,258,7726/1966 Humpherys ..343/l7.l R

j IDENTIFICATION CIRCUIT T 2=(TTT/2L m b 14/4, Tl z DELAY b DELAY J b EU CIRCUIT ClRCUIT AND D L Q A D2 AND RESPONDED WAVE \Q R l R1 F962 FR FR.PATENTEDDDT 10 I972 3.697.991 SHEET 010! 12 Z i j 7' SYNCHRONIZATION 7'SECONDARY TRANSMITTER A REcEIvER QEP WQ 8 IQ/ER PRIMARY RADAR L QRECEIVER N IDENTIFICATION INDIcATOR A- CIRCUIT j IDENTIFICATION CIRCUITT Z=(TT-TQL, T/ DELAY MEAZKL b E CIRCUIT 3-. A U

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l 55: R LET NH u= E LET QLNQ SEQ gs E H 'mN mvawoas 0,4 wry/4 PMENTEDW10 m2 sum 10 or 12 9 L 7 gm gq E E 5 33; i i? sm qf m m m fi i i? E: E,ig i j $31. QE EE E. A53} mai m n u g gq ws q ma LIMA i u w JfiWF I MEML3 ELL in. mm 9% fiL fi E E M t i PMENTEDIJBI 10 1912 SHEET lEUF 12 mwm t4 0/24 K4w 4s/065 7 K50 M K4540) W ATTORNEYS B Y @M/ W SECONDARY RADARRECEPTION SYSTEM BACKGROUND OF THE INVENTION This invention relates to asecondary radar reception system, that is, the so-called transponderreception system which receives on the side of a primary radar aresponded wave transmitted or emitted from a secondary radar in responseto a radar pulse from the primary radar and containing a response pulseand an identification pulse delayed a predetermined time behind theresponse pulse, and produces a multiplied output of the response pulseand the identification pulse and indicates the distance and azimuth ofthe secondary radar relative to the primary radar based upon themultiplied output.

SUMMARY OF THE INVENTION The primary object of this invention is toprovide a secondary radar reception system which is simple inconstruction and accurate in operation.

Another object of this invention is to provide a secondary radarreception system which is provided with a special identificationcircuit.

Other objects, features and advantages of this invention will becomeapparent from the following description taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a systematic diagram forexplaining a secondary radar reception system of this invention;

FIG. 2 is a systematic diagram showing one example of this invention;

FIGS. 3A-3L are signal waveform diagrams for explaining the system shownin FIG. 2;

FIG. 4 is a systematic diagram illustrating another example of thisinvention;

FIGS. SA-SL are signal waveform diagrams for explaining the systemexemplied in FIG. 4;

FIG. 6 is a further example of this invention;

FIGS. 7A-7L are signal waveform diagrams similar to FIGS. 3A3L;

FIGS. 8A-8L are signal waveform diagrams similar to FIGS. SA-SL;

FIG. 9 is a systematic diagram illustrating still a further example ofthis invention; and

FIGS. MIA-10L are signal waveform diagrams for explaining the systemdepicted in FIG. 9.

DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 1 reference numeral 1indicates generally a primary radar which includes an antenna 2, atransmitter-receiver 3, a radar indicator device 4 and a synchronizationcontrol circuit 5 and provides planposition indication on a display tubeof the indicator device 4.

Reference numeral 6 designates generally a receiver device which isprovided on the side of the primary radar l for receiving an electricwave emitted from a secondary radar (not shown). The receiver device 6comprises an antenna 7 for receiving a responded from the secondaryradar which consists of a response pulse and identification pulsesdelayed a predetermined time behind the response pulse emitted inresponse to the reception of a radar pulse transmitted from the primaryradar 1, a secondary radar receiver 8 for deriving the aforesaidresponded wave received by the antenna 7 and a secondary radaridentification circuit 9 which derives a multiplied output of theresponse pulse and the discriminating pulse of the response wave fromthe output of the receiver 8 and is controlled by a synchronizing signalfrom the synchronization control circuit 5 for discriminating thesecondary radar signals from others. In the present example themultiplied output of the response pulse and the identification pulses ofthe responded wave produced by the identification circuit 9 is suppliedto the indicator device 4, thereby to indicate on its display tube thedistance of the secondary radar from the primary radar, the azimuth ofthe former relative to the latter and so on.

Since the foregoing construction is well-known in the art, no furtherdetailed description will be given. The present invention relates to thefollowing construction of the identification circuit 9 for deriving themultiplied output of the responded pulse and the identification pulsescontained in the responded wave from the output of the receiver 8receiving the responded wave from the secondary radar.

Let it be assumed for convenience of explanation that the radar pulseemitted from the antenna 2 of the primary radar l is a pulse such asindicated by PT in FIG. 3A which has a period TT and that the output ofthe receiver 8 corresponding to the responded wave emitted from thesecondary radar in response to the radar pulse PT and received by thereceiver 8 is a pulse such as indicated by PR in FIG. 3B which consistsof a response pulse A delayed behind each pulse PT by a time T0corresponding to the distance between the primary radar and thesecondary radar and a discriminating pulse Bl delayed behind the pulsePR by a predetermined time T1. In this invention as shown in FIG. 2 theidentification circuit 9 includes a first multiple delay circuit D, fordelaying the responded wave by the time T1 corresponding to the timebetween the identification pulse B1 and the response pulse A, a secondmultiple delay circuit D: for providing a delay of a time T2 which is adifference between the period of the responded pulse A, that is, theperiod TT of the radar pulse and the time T2 (T2 TT- Tl multipliercircuits Ala and A2a of the and circuit construction respectivelyprovided on the input sides of the delay circuits D and D an or circuitOR provided on the input side of the multiplier circuit Ala and an andcircuit E provided on the output side of the delay circuit D In thepresent invention the responded wave PR shown in FIG. 3B, which isderived at a terminal U connected to the output side of the secondaryradar receiver 8, is supplied to the one input terminal a of each of thefirst and second multiplier circuits Ala and A2a. The output of themultiplier circuit Ala is applied to the input side of the firstmultiple delay circuit D,, the output of which is, in turn, supplied tothe other input terminal b of the second multiplier circuit A2a.Further, the output of the second multiplier circuit A2a is fed to theinput side of the second multiple delay circuit D the output of whichis, in turn, applied to the other input terminal b of the firstmultiplier circuit Ala through the or circuit OR and, at the same time,to one input terminal b of the and" circuit E.

In this case the multiple delay circuits D and D are of theshift-register construction. At a terminal FQ connected to thesynchronization control circuit 5, a clock pulse Q such as shown in FIG.3C (synchronized with the radar pulse PT) is provided. The clock pulse Qis supplied to the multiple delay circuits D and D to sequentially shiftthem. At a terminal FR connected to the synchronization control circuit5 there is produced a rectangular wave R such as shown in FIG. 3D whichis 1 for one period TT of the radar pulse PT, for example, every threeperiods 3TT of the radar pulse in synchronization therewith and therectangular wave R is applied through the or circuit OR to the inputterminal b of the multiplier circuit Ala. At a terminal FR connected tothe synchronization control circuit 5 there is obtained a rectangularwave R such as shown in FIG. 3E which is l for a time of, for example,TT/2 in synchronization with the radar pulse PT in the period duringwhich the rectangular wave R is l, and the rectangular wave R is appliedto one input terminal a of the and circuit E.

The period 3TT of the rectangular waves R and R will hereinafter bereferred to as a multiplying period TM and the period TT during whichthe rectangular waves R and R are 1" in the period TM. The subsequentperiod TT and the last period TT will hereinafter be referred to asfirst, second and third periods. Further, the response pulse A and theidentification pulses Bl which are respectively obtained in theseperiods will be identified as A1, A2, A3 and B11, B12, B13 respectively.With the arrangement described above, in the first period the inputterminal b of the multiplier circuit Ala is supplied with the input Ibased upon the output l of the rectangular wave R irrespective of theoutput content of the second multiple delay circuit D so that theresponse pulse Al and the identification pulse B1 1 of the respondedwave PR from the terminal U are derived at the multiplier circuit Ala inthe first period as illustrated in FIG. 3F and the resulting pulses aresequentially fed to the first multiple delay circuit D As a result ofthis, thefirst multiple delay circuit D produces a response pulse Al andidentification pulse B11 such as depicted in FIG. 36 which arerespectively delayed behind those A1 and B11 by the time T1 and theresulting pulses are applied to the input terminal b of the multipliercircuit A2a.

The input terminal a of the multiplier circuit A2a is always suppliedwith the responded wave PR without delay, so that the circuit A2aproduces an output A1-B1l such as shown in FIG. 3H which is obtained bymultiplication of the identification pulse B11 with the delayed responsepulse A1 of FIG. 36 in the first period.

The multiplied output A1811 is supplied to the second delay circuit D toderive therefrom an output which has been delayed behind the originalmultiplied output Al-Bll by the time T2 (T2 TT- Tl) as shown in FIG. 3].In this case the delayed multiplied output AlBll is produced in thesecond period and the output of the rectangular wave R is in the secondperiod, so that the delayed multiplied output AlBll is supplied to theinput terminal b of the first multiplier circuit Ala.

In this manner, the delayed multiplied I output A1811 is applied to theinput terminal b of the first multiplier circuit Ala but its other inputterminal a is always supplied with the response wave PR, so that themultiplier circuit Ala produces an output A1-B11A2 such as depicted inFIG. 3F which results from multiplication of the response pulse A2 inthe second period by the multiplied output Al'Bl 1.

The resulting multiplied output A1-B1 l-A2 is applied to the first delaycircuit D and is thereby delayed by the time T1 and the delayedmultiplied output Al-Bl 1- A2 is multiplied by the discriminating pulseB12 of the second period in the multiplier circuit A2a, thus producing amultiplied output Al'Bll'AZ'BlZ such as illustrated in FIG. 3H. Themultiplied output thus produced is delayed by the delay circuit D and issupplied through the or" circuit OR to the multiplier circuit Ala whichproduces an output A1'Bll'A2'B12-A3 resulting from multiplication of theresponse pulse A3 of the third period by the delayed multiplied outputA1-B11-A2-B12. The resulting multiplied output Al-Bll'A2'Bl2A3 isdelayed by the delay circuit D and is multiplied by the identificationpulse B13 in the multiplier circuit A2a and is then delayed by the delaycircuit D thus producing a delayed multiplied outputAl'Bll'A2'Bl2'A3'B13. This multiplied output is produced in the firstperiod subsequent to the multiplication period TM, and hence is maskedby the output l of the rectangular wave R.

Then, in the following multiplication period TM exactly the sameoperations as those above described are repeatedly performed.

The output of the delay circuit D depicted in FIG. 3I is applied to theinput terminal b of the and circuit E, and the other input terminal a ofwhich is supplied with the rectangular wave R during the first period TTof the multiplication period TM. Consequently, there is produced at theoutput terminal U of the and circuit E an and output PR such as shown inFIG. 3] which is composed of the multiplied output Al-Bll-AZ- Bl2-A3-B13and the rectangular wave R.

The output PR thus obtained is applied as the output of theidentification circuit 9 to the indicator device 4 to indicate on itsdisplay tube the distance of the secondary radar from the primary radarand the azimuth. The distance and azimuth determine the position of thesecondary radar.

In the secondary radar discriminator circuit exemplified in FIG. 2 theresponded wave PR is supplied to the first multiple delay circuit Dthrough the and circuit Ala, the output of the delay circuit D, and theresponded wave PR are supplied to the second multiple delay circuit Dthrough the and circuit A2a and the output of the delay circuit D andthe rectangular wave R are applied to the output terminal U through theand circuit E. Consequently, even if noise is contained in the respondedwave PR, the second and circuit A2a inhibits the passage therethrough ofthe noise, so that substantially no noise is contained in the outputapplied to the output terminal U, thus ensuring accurate detection ofthe secondary radar.

While this invention has been above described in connection with thecase where the responded wave PR consists of the response pulse A andone identification pulse B1 in one period TT of the radar pulse, theinvention is applicable to the case where in one period of the radarpulse the response wave PR consists of one response pulse A, a firstidentification pulse Bl delayed a predetermined time T1 behind theresponse A, a second identification pulse B2 delayed a predeterminedtime T2 behind the first identification pulse B1, and an nthidentification pulse Bn delayed a predetermined time Tn behind a (n l)thidentification pulse B(n I), that is, ns identification pulses B1, B2,Bn as a whole. This involves the provision of a first delay circuit D,of the time T1 a second delay circuit D of the time T2, an nth delaycircuit D,, of the time Tn and a (n l)th delay circuit D of the time T(nl) corresponding to a time {Tr (Tll T2 Tn)}, that is, (n +l )s delaycircuits D D D as a whole and the provision of first, second, (n l)thmultiplier circuitsAla, A2a, A(n l)a', that is (n l)s multipliercircuits as a whole. In such a case, the responded wave PR and theoutput of the (n l)th delay circuit D are multiplied together by thefirst multiplier circuit Ala, whose output is applied to the first delaycircuit D,, the responded wave PR and the output of the first delaycircuit D, are multiplied together by the second multiplier circuit A2a,whose output is applied to the second delay circuit D the responded wavePR and the output of the nth delay circuit D,, are multiplied togetherby the (n l)th multiplier circuit A whose output is fed to the (n l)thdelay circuit D,,,,,,; and a multiplied output of the response pulse Aand the ns identification pulses B1, B2, Bn in the responded wave PR isderived from the (n l)th delay circuit D In the foregoing n is apositive integer.

FIG. 4 shows another example of this invention as being applied to thecase where the number of the discriminating pulses in the responded wavePR is two, that is, n 2. Although no detailed description will be givenof the illustrated discriminator circuit, its construction andoperational effect will be seen from FIGS. 4 and S. In the presentexample the multiplication period TM is 3TT as is the case with theforegoing example. Two identification pulses BI and B2 in the firstperiod TT of the multiplication period TM are respectively indicated byB11 and B21 and two identification pulses B1 and B2 in the second periodand two identification pulses B1 and B2 in the third period arerespectively denoted as B12, B22, and B13, B23. FIGS. 5A to 5B show thesame signals as those depicted in FIGS. 2A to 2E, that is, a radar pulsePT, responded pulses PR, a clock pulse Q, and rectangular signals R andR. FIGS. 5F to SL respectively illustrate outputs of a multipliercircuit Ala, a delay circuit D a multiplier circuit A2a, a delay circuitD a multiplier circuit A3a, a delay circuit D and an and circuit E.

As has been described in the foregoing, the present invention makes iteasy to obtain the multiplied output of the response pulse and theidentification pulse contained in the responded wave PR. The inventionrequires one more delay circuit than the number of identification pulsesbut the overall time necessary for the operation of the delay circuitscorresponds to the period of the radar pulse, so that the overallconstruction of the identification circuit of this invention can beproduced at low cost. Further, if the multiplication period TM isselected to be NTM (N being a positive integer more than 2), themultiplication of the response pulse and the identification pulse isequivalent to the number of multiplications equal to N for eachmultiplication period, and, in the example of FIG. 4, the two andcircuits A2a and A311 are incorporated into the delay circuit as in theexample of FIG. 2 to inhibit the passage therethrough of noise containedin the response wave, so that an accurate multiplied output of theresponse pulse and the identification pulse can be produced to preciselyobtain the distance of the secondary radar from the primary radar andits azimuth.

In the foregoing the multiple delay circuits are of the shift registerconstruction which are driven by the clock pulse Q but the delaycircuits may be replaced with, for example, delay lines capable ofproviding a delay without being driven by a clock pulse.

The foregoing description has been made on the assumption that where themultiple delay circuits are driven by the clock pulse Q, the rise-uptimes of the response pulse and the identification pulse of theresponded wave PR coincide with that of the clock pulse. In practice,however, at times the rise-up times of the response pulse and theidentification pulse will be different from that of the clock pulse. Inthis case if the responded wave PR precedes by a short time 1' that inthe case of FIG. 3B as shown in FIG. 3B in the case of FIG. 2, theresponse pulse A1 and the identification pulse B11 obtained in themultiplier circuit Ala in the first period of the radar pulse PT of theperiod TM are earlier by the time T than those shown in FIG. 3F asillustrated in FIG. 3F but the outputs produced by the multipliercircuit Ala, the delay circuit D,, the multiplier A2a, the delay circuitD and the and circuit E agree with the rise-up time depicted in FIGS. 3Fto 3] as illustrated in FIG. 3F to 3], with the result that an output PRis delayed by the time 1 behind the response pulse. This introduces inthe indication of the position of the secondary radar an errorcorresponding to the time 1'.

In practice, such an error can be made negligible by minimizing theperiod T of the clock pulse Q and increasing the bit number of the delaycircuits correspondingly. However, where the bit number of the delaycircuits is limited to a certain value, an output at the bit positionimmediately before the last one of the last delay circuit, namely thedelay circuit D in FIG. 2 is multiplied by the response wave and theresulting multiplied output is utilized as an input to the indicatordevice 4.

FIG. 6 illustrates another example of this invention which is adapted toeliminate an error such as occurs when there is one discriminating pulseof the responded wave PR as in the case of FIG. 2. In the presentexample parts corresponding to those in FIG. 2 are identified by thesame reference numerals and no detailed description will be repeated. Inthe figure a multiplier circuit E is provided in place of the andcircuit E of FIG. 2 and the output at an (n l)th bit position of thelast delay circuit D consisting of ns bits is supplied to an inputterminal 11 of the multiplier circuit E, while the responded wave PRderived from the terminal U and the rectangular wave R from the terminalFR are respectively applied to the other input terminals a and c of themultiplier circuit E. However, the output of the delay circuit D fed tothe multiplier circuit Ala is produced at the last bit position, thatis, at the nth bit position of the delay circuit D Thus, there isproduced at the (N 1)th bit position of the delay circuit D an outputsuch as depicted in FIG. 3K which is advanced by one bit time, that is,one period T of the clock pulse Q further than the output of the delaycircuit D that is, the output at the Nth bit position shown in FIG. 31and 31'. As a result, the multiplier circuit E produces an output PR"such as shown in FIG. 3L which rises up at the time when the responsepulse A of the responded wave PR is produced. Consequently, the positionof the secondary radar can be indicated on the indicator tube of theindicator device 4 without the aforementioned error.

If there are n identification pulses, the indication can be providedwithout error.

Further, the identification circuit of this invention can be constructedin such a manner as to obtain a multiplied output of the output of thedelay circuit at its (n 1 )th bit position and the response pulse of theresponded wave without applying the rectangular signal R to themultiplier circuit E.

Although the foregoing description has been made in connection with thecase where the radar pulse emitted from the primary radar 1 has theperiod TT and the delay of the period TT is produced by the overallseries connection of the delay circuits employed, the pulse intervals ofthe radar pulse need not to be of the same period TT and, the radarpulse is only required to be periodic. In this case the circuitconnections are such that after a predetermined number of shift pulses Qis continuously produced for each radar pulse for a time TL and thedelivery of the shift pulse Q is rendered intermittent to enable a delayof the time TL to be produced by the series connection of the delaycircuits. In the example above described with FIG. 2 the delay time T2of the delay circuit D is selected such that T2 TL T1 and in the exampleof FIG. 4 the delay time T3 of the delay circuit D is similarly selectedsuch that T3 TL (Tl T2). FIG. 7 shows signals appearing at therespective circuit point corresponding to those in FIG. 4 when the delaytime T2 of the delay circuit D has been selected as T2 TL T1 in FIG. 2and FIG. 8 illustrates signals produced at the respective circuit pointscorresponding to those in FIG. when the delay time T3 of the delaycircuit D, has been selected as T3 TL (T1 T2) in FIG. 4. It is a matterof course to effect other various modifications and variations.

FIG. 9 illustrates another modification of the secondary radaridentification circuit 9 of this invention. The following descriptionwill be made on the assumption that a radar pulse PT emitted from anantenna 2 of a primary radar l is obtained at time intervals TT as shownin FIG. 10A, also, that an output PR1 of a receiver 8 receiving aresponded wave emitted from a first secondary radar in response to theradar pulse PT consists of a first response pulse AlA delayed behind theradar pulse PT by a time T10 corresponding to the distance between theprimary radar and the first secondary radar and a first discriminatingpulse B1B delayed behind the response pulse AIA by a predetermined timeT11 as depicted in FIG. 1081. Also, that an output PR2 of the receiver 8receiving an responded wave emitted from a second secondary radarconsists of a second response pulse A2A delayed behind the radar pulsePT by a time T20 corresponding to the distance between the primary radarand the second secondary radar and a second identification pulse B2Bdelayed behind the second response pulse AZA by a predetermined time T21as depicted in FIG. 1082. The widths of the first and second responsepulses AIA and A2A are respectively indicated by TPl and TP2 and thoseof the first and second discriminating pulses B1B and B2B arerespectively designated by TPl and TP2. For convenience, these pulsewidths are selected such that TPl TP2 TPl' TP2 TP. Assume that the widthTP has a longer time duration than a bit unit time T shown in FIG. 10Cof a delay circuit which will be described later. Further, let it beassumed that the difference between the delay time T1 1 and T21 'issmaller than the pulsewidth TP but greater than the bit unit time T Insuch a case the discriminator circuit 9 examplified in FIG. 9 includes adelay circuit DL having first to nth bit elements D D D each providing apredetermined delay time TL which is shorter than the shortest possibletime between adjacent pulses of the radar pulse PT shown in FIG. 10A.The bit elements D D D,,,, of the delay circuit DL are connectedtogether in the form of a shift register and the delay circuit DL isdriven by n clock pulses Q which are sequentially produced at timeintervals of the bit unit time T for each radar pulse PT insynchronization therewith, as shown in FIG. 10C, which is supplied to aterminal FQ connected to a synchronizing signal source 5. Consequently,the overall delay time TL of the delay circuit DL is given by TL T 'nwith n being naturally a positive integer.

The input side of the first bit element D of the delay circuit DL isconnected to an output side g13 of a multiplier circuit G1 of the andcircuit construction and the one input terminal gll of the multipliercircuit G1 is connected to a terminal U connected to the output side ofthe secondary radar receiver 8. Further, the output side of the nth bitelement D of the delay circuit DL is connected to the one input terminalof an or circuit ORA and to the one input terminal c1 of an and circuitEA and the output side of the or circuit ORA is connected to the otherinput terminal g12 of the multiplier circuit G1 and the output terminale3 of the and circuit EA is connected to an output terminal U. Theoutput terminal U is connected to the radar indicator device 4 shown inFIG. 1.

A multiplier circuit G2 is interposed between a Qth bit element D and a(Q 1th bit element D the bit element D corresponding to the greatestpossible number Q (Q (TP TC)/T 0 and is an integer smaller than n) ofthe bit unit time T capable of satisfying the time TQ which is smalleror equal to the difference (TP T between the pulse width TP of each ofthe first and second response waves and the bit unit time T that is, TTQ (TP T and the multiplier circuit G2 having its one input terminal g22connected to the output side of the 0th bit element Dq the other inputterminal g2] connected to the terminal U and its output terminal g23connected to the input side of the (Q 1)th bit element D If TP 4T TQ canbe made to be 2T or 3T and accordingly Q is 2 or 3 because T TQ (TP- TIf TQ is 2T Q is 2, so that the Qth bit element D is D and the bitelement D is D as illustrated in FIG. 9. Consequently, between the bitelements D and D is interposed the multiplier circuit G2 having its oneinput terminal g22 connected to the output side of the bit element D theother input terminal g2l connected to the terminal U and the outputterminal g23 connected to the input side of the bit element D Further, amultiplier circuit H1 of the and circuit construction is interposedbetween a jth bit element D and a (J l)th bit element D the bit elementD producing an output delayed behind that of the first bit element D bya time T1] which is the delay time between the response pulse AIA andthe discriminating pulse 818 of the first response wave PR1 and themultiplier circuit H1 having its one input terminal h12 connected to theoutput side of the jth bit element D the other input terminal hllconnected to the output side of an or circuit ORl described later andthe output terminal h13 connected to the input side of the (j l)th bitelement D In addition, another multiplier circuit H2 of the and" circuitconstruction is connected between a kth bit element D and a (k l)th bitelement D the bit element D producing an output delayed behind that ofthe first bit element D by a time T21 which is the delay time betweenthe response pulse A2A and the discriminating pulse B2B of the secondresponse wave PR2 and the multiplier circuit H2 having its one inputterminal h22 connected to the output side of the kth bit element D theother input terminal h21 connected to the output side of an or circuitR2 described later and the output terminal h23 connected to the inputside of the (k l)th bit element D In the delay circuit DL the outputside of the first bit element D is connected to the input side of thesecond bit element D the bit elements D D D, are cascaded, the bitelements D D )a..... D are similarly cascaded and the bit elements D D Dare likewise cascaded. Accordingly, in the delay circuit DL the bitelements are arranged in the Ordfir Of D1 D2 "Da Dm-Du+n Dk *DUH. D andthe multiplier circuits G2, H1 and H2 are respectively interposed in acascade connection between the bit elements D and D and also between Dand D and between D and D The clock pulse 0 as shown in FIG. 10C issupplied from the terminal FQ to a delay circuit DL comprised of the bitelements D to D,,,,. The delay circuit DL provides a total delay time TL(TL= n'T At the terminal FR connected to the synchronizing controlcircuit 5 there is derived a rectangular wave R1 such as depicted inFIG. D which is produced every third radar pulse PT in synchronizationtherewith and has a width corresponding to the intervals between twoadjacent radar pulses PT, the resulting rectangular wave R being appliedthrough the or" circuit ORA to the input terminal g12 of the multipliercircuit G1. Further, at the terminal FR connected to the synchronizationcontrol circuit 5 there is derived a rectangular wave R1 such as shownin FIG. 10E which is produced every third radar pulse PT insynchronization therewith and has a width of, for example, 'rTT smallerthan the period T)" between adjacent radar pulse PT, the rectangularwave R1 being fed to an input terminal e2 of the and circuit EA.

In FIG. 9 reference characters WA, WB and WC designate ganged switches.The terminal U is connected to the input terminal hll of the multipliercircuit H1 through a moving contact c1 and a fixed contact al of theswitch WA and the or circuit CR1 and, at the same time, the terminal Uis connected to the input terminal h21 of the multiplier circuit H2through the moving contact cl and a fixed contact bl of the switch WAand the or circuit 0R2. At, the terminal FC a control output I alwaysoccurs because the logic is such that the signal FC is 1. Terminal FC isconnected through a fixed contact b2 and a moving contact 02 of theswitch WB to the or" circuit CR1 and further to the input terminal hllof the multiplier circuit H1 while being, at the same time, connectedthrough a fixed contact A3 and a moving contact 03 of the switch WC tothe or circuit CR2 and further to the input terminal 1121 of themultiplier circuit H2.

A description will be given of the operation of the discriminatorcircuit 9 of the above construction on the assumption that the movingcontacts C1, c1, c2 and c3 of the switches WA, WB and WC lie on thecontacts a1, a2 and a3 as illustrated in FIG. 9 during the reception ofthe first response wave from the first secondary radar. Let it beassumed that the period between the radar pulse and a pulse adjacentthereto in which the rectangular wave R1 is produced is a first period,that the periods between the following adjacent pulses are second andthird periods and that these three periods repeat. If the output l ofthe rectangular wave R1 is produced in the first period, the inputterminal g12 of the multiplier circuit G1 is supplied with an input Ibased upon the output 1. Consequently, in the first period themultiplier circuit G1 derives therefrom the response pulse AIA and thediscriminating pulse 818 of the response wave PR1 from the terminal U asshown in FIG. 10F1 and these pulses are sequentially applied to the bitelement D of the delay circuit DL. As a result, there is obtained at theoutput side of the Qth bit element D in the example of FIG. 9 the bitelement D pulses AIA and 818 such as shown in FIG. 10Gl which aredelayed behind those A1A and B18 in the first period depicted in FIG.10F l by two bit times ZT and the resulting pulses are supplied to theinput terminal g22 of the multiplier circuit G12.

The other input terminal g21 of the multiplier circuit G2 is suppliedwith the response wave PR1 from the terminal U, so that the multipliercircuit G2 produces multiplied outputs A1A and B1B of the pulses AIA and81A in the first periods of FIGS. 10131 and 1061 as shown in FIG.101-11. If the widths of the multiplied outputs AIA and B1B arerespectively taken as Trl and Trl, Trl TPl 2-T and Trl TPl' 2-T Thesewidths are narrower than those of the pulses AIA and 318. The multipliedoutputs AIA and 818 are respectively produced at times (T10 Z'T and (T10Z'T T11).

Then, the multiplied outputs AIA and B1B depicted in FIG. 10H1 areapplied to the (Q l)th bit element D in the example of FIG. 9 the bitelement D to produce multiplied outputs AIA and 8113 such as depicted inFIG. 1011 which are respectively delayed by the time T11 behind thepulses AIA and 818 of the first period of FIG. mm, and the resultingmultiplied outputs are sequentially supplied to the input terminal hl2of the multiplier circuit H1.

The other input terminal hl 1 of the multiplier circuit H1 is suppliedwith the response wave PR1 from terminal U through the moving contact cland fixed contact al of the switch WA and through the or circuit R1which has no delay. The multiplier circuit H1 produces a multipliedoutput A1A 'BlB from the pulse 818 of FIG. 1031 and the multipliedoutput AlA from the first period as shown in FIG. Il.

The multiplied output AlA' 'BlB is applied to the (j 1 )th bit elementDUN) and, the input terminal 1221 of the multiplier circuit H2 issupplied with the output 1 from the terminal FC through the fixedcontact a3 and the moving contact c3 of the switch WC and the or circuit0R2, so that the multiplied output A1A 'B1B is applied through themultiplier circuit H2 to a bit element D and is stored and memorized inbit elepreceding the bit element D,,,, by numbers represented y D T10and D and n l-1,

thus completing the first period. In the second period the output AlA'BlB stored in the first period is transferred by the clock pulseproduced with the radar pulse PT as the reference, with the result thatafter a time T10 from the starting time the bit element D produces asits output the multiplied output A1A 'BlB having a width (TP 2'T at thetime when the pulse AlA of FIG. 1031 in the second period is produced.This is shown in FIG. 10K1. When the output of the rectangular wave R1is 0 during the second period, the multiplied output AlA BlB shown inFIG. 10Kl is supplied to the input terminal gl2 of the multipliercircuit G1.

In this manner, the multiplied output AlA 'B1B shown in FIG. 10Kl isapplied to the input terminal gl2 of the multiplier circuit G1, whilethe response wave PR1 is supplied to the other input terminal gll of thecircuit G1. Accordingly, the multiplier circuit G1 produces a multipliedoutput AlA -BlB of the pulse AIA and the multiplied output AlA -BlB inthe second period as illustrated in FIG. IOFl.

Then, the multiplied output A1A 'B1B is applied to the first bit elementD and the Qth bit element D produces a multiplied output AlA 'B1B suchas shown in FIG. l0G1 which is delayed behind the original multipliedoutput AlA -BlB by the time 2'T and the delayed multiplied output AlA'BlB is applied to the multiplier circuit G2. While, the multipliercircuit G2 is supplied with the response wave PR1, and hence produces amultiplied output AIA 'BIB depicted in FIG. 10H] which results frommultiplication of the pulse AlA of the second period and the multipliedoutput AlA""BlB of FIG. 10G1. This multiplied output AlABIB is delayedby the jth bit element D as shown in FIG. 1011 and is then applied tothe multiplier circuit H1 of FIG. 9. The multiplier circuit H1 issupplied with the response wave PR1, and produces a multiplied outputAlA-B1B such as shown in FIG. 10.11 which results from multiplication ofthe pulse B1B of the second period and the multiplied output AlA 'BlBdepicted in FIG. 1011. This multiplied output AlABlBis applied to bitelements preceding the bit element D designated by and the appliedoutput is thereby memorized, thus completing the second period.

In the third period of delayed output A1A-B1B is applied from the bitelement D through the or circuit ORA to the multiplier circuit G1 in thesame manner as in the second period, from which circuit is derived amultiplied output AlA -B1B resulting from multiplication of the pulseAlA of the third period and the multiplied output MAJ-B1B depicted inFIG. 10K1. The resulting multiplied output A1A -B1B is delayed by thebit element Dq as depicted in FIG. 10Gl and is fed to the multipliercircuit G2, from which is derived a multiplied output AlAl'BlB such asillustrated in FIG. 10111 which results from multiplication of theoutput AlA 'BlB. shown in FIG. 10G1 and the pulse AlA of the thirdperiod. The multiplied output AlA -B1B is delayed by the bit element Das shown in FIG. 1011 and is supplied to the multiplier circuit H1, fromwhich is derived a multiplied output AlA -BlBsuch as shown in FIG. 10Jlresulting from multiplication of the pulse B1B of the third period andthe multiplied output A1A 'BlB The resulting multiplied output AlA -B1Bis memorized by predetermined bit elements as in the previous periodsand the third period is thus completed. In a first period subsequent tothe above third period the multiplied output AlA -BlBis caused to startits transfer by the clock pulse starting with the radar pulse PT and isobtained after the elapse of time T10 from the starting time as depictedin FIG. 10Kl.

The multiplied output AIA -BIB of the subsequent first period shown inFIG. 10K1 is to be applied to the multiplier circuit G1 through the orcircuit ORA. However, in this first period the rectangular wave R1 isapplied to the multiplier circuit G1 through the or circuit ORA, therebyinhibiting the application of the multiplied output A1A"'-B1B to themultiplier circuit G1.

Thus, the operations above described are repeatedly carried out toproduce the multiplied output AlA -BlB 3 during each first period.

The multiplied output AlA -I3lB produced in each first period issupplied to the input terminal c1 of the and circuit EA and, on theother hand, the output 1 of the rectangular wave R1 of the first periodis applied to the other input terminal e2, thereby deriving at theoutput terminal e3 an output PR1 based upon the multiplied output AlA-BlB as illustrated in FIG. 3L1.

The resulting output PR1 is applied to the indicator device 4 as anoutput of the discriminator circuit 9, and the distance and azimuth ofthe first secondary radar are indicated on the display tube of theindicator device 4.

The foregoing description has been given for the reception of the firstresponse wave of the first secondary radar. For the reception of thesecond response wave from the second secondary radar the moving contactsc1, c2 and c3 of the switches WA, WB and WC are respectively moved downto the contacts bl, b2 and b3 and the multiplier circuit H2 is used inplace of the circuit H1 or vice versa. Accordingly, the same operationsas described above are carried out by replacing the multiplier circuitH1 with H2 and H2 with H1, the response wave PR1 with PR2, the pulsesAIA and B1B with A2A and B2B, the bit elements D and D with D and D theor circuit R1 with CR2 and the times T and T11 with T and T21 in theforegoing. Thus, an output PR2 based upon a multiplied output A2A 'B2Bisderived at the output terminal U of the and circuit EA. The output issupplied to the indicator device 4 to indicate on its display tube thedistance and azimuth of the second secondary radar with respect to theprimary radar. For the sake of brevity, the waveforms appearing at therespective circuit elements in the reception of the response wave fromthe second secondary radar, which correspond to those in the receptionof the response wave from the first secondary radar shown in FIGS. 10F1to 10L1, are illustrated in FIG. 10F2 to 101.2 and no further detaileddescription will be given of the operations in the reception of theresponse wave from the second secondary radar.

As will be apparent from the foregoing, the present example shown inFIG. 9 enables satisfactory reception of both of the first response waveof the first secondary radar and the second response wave of the secondsecondary radar through the use of the discriminator circuit 9.

In accordance with this invention, even if the second (or first)response wave from the second (or first) secondary radar has arrived atthe discriminator circuit 9 during the reception of the first (orsecond) response wave from the first (or second) secondary radar, nomultiplied output based upon the second (or first) response wave isderived at the output terminal U. This is true not only in the casewhere the difference (Tll T21) between the time difference T11 betweenthe response pulse AIA and the discriminating pulse B1B of the firstresponse wave from the first secondary radar and the time difference 721between the response pulse A2A and the discriminating pulse B2B of thesecond response wave from the second secondary radar is greater than thepulse width TP of each of these pulses but also in the case where thetime difference (T11 T21) is smaller than the pulse width TP. This istrue so long as the time difference (T11 T21) is greater than the bitunit time T of the clock pulse Q.

This is because in the present invention the multiplier circuit G2 isinterposed between the Qth bit element B and the (Q l)th bit element Dand a pulse of narrow width, in the foregoing example the pulse AlA of awidth (TP Z-T is derived from the multiplier circuit G2 in response tothe response pulse AlA (or 818) of the first period at the time when theresponse pulse is obtained. The time difference (T11 T21) between thepulses AIA and B1B of the first response wave PR1 and the timedifference between the pulses A2A and 1828 of the second response wavePR2 is such that T (Tl1 T12) TP. This will hereinbelow be explained onthe assumption that the second response wave has reached thediscriminator circuit during the reception of the first response wave.

In this case the second response wave PR2, shown in FIG. 1082 is appliedto the multiplier circuit G1 in the first period as previouslydescribed, from which circuit are derived pulses A2A and 828 as depictedin FIG. IOFZ. While, the bit element D produces pulses A2A and 823 suchas shown in FIG. 10G2 which are delayed by the time 2-T behind thepulses A2A and B2B depicted in FIG. 10F2'. The delayed pulses A2A andB2B are supplied to the multiplier circuit G2, while the response wavePR2 shown in FIG. 1032 is fed to the multiplier circuit G2, so thatpulses AIA and B1B, each having a width (TP Z-T are obtained at the timewhen the pulses A2A and B2B depicted in FIG. 10G2' are produced, asshown in FIG. 10H2' and these pulses AIA and B1B are derived at theoutput side of the (j l)th bit element D, at a time delayed by T11behind the time when the pulse A2A depicted in FIG. 10B2 is produced, asillustrated in FIG. 1012, and then the resulting pulses are applied tothe multiplier circuit H1. However, the pulse A2A of FIG. 1082 is notproduced in the period in which the pulse A1A of F I6. 1012 is produced,as shown in FIG. 1012' ((T11 Tl2) 2-T so that no multiplied output isderived from the multiplier circuit H1. This results in that nomultiplied outputs are produced in the following second and thirdperiods as illustrated in FIGS. 10K2' and 10L2'.

In the event that the multiplier circuit G2 interposed between the Qthbit element D and the (Q l)th bit element D is left out and insteadthese bit elements are directly cascaded in the example of FIG. 9, ifthe second (or first) response wave has come during the reception of thefirst (or second) response wave, a multiplied output based upon thesecond response wave is produced.

Accordingly, in the present invention, if the widths of the responsepulse and the discriminating pulse are constant in the establishment ofthe time difference between the response pulse and the discriminatingpulse of the response wave from the secondary radar, the time differencebetween the response pulse and the discriminating pulse can be selectedto be large, so that even when there are many secondary radars, theirpositions can be discriminated. Further, when the number of thesecondary radars is definite, the pulse interval of the radar pulse fromthe primary radar is selected to be short to enable many repeatingnumbers of the response waves from the secondary radars, to be obtainedso that the azimuth and distances to the secondary radars can beaccurately obtained.

Although the foregoing description has been given in connection with thecase where the relationships between the widths TPI and TH of theresponse pulse AIA and the discriminating pulse B1B of the firstresponse wave and those TP2 and TP2 of the response pulse A2A and thediscriminating pulse B2B of the second response wave are selected suchthat TPl TP2 TPl' TP2 TP, is is also possible that TPl TP2 and that TPlTP2. In this case the aforesaid number Q is calculated on the assumptionthat TPl TP2 TP and the bit elements between which the multipliercircuit G2 is to be interposed are determined on the calculated Q.However, it is necessary that TP1 Q-T and that TP2' Q'T It is alsopossible to select pulses such that TPl' TP2 and that TPl at TP2 inwhich case Q is calculated based on TPl TP2 TP and the position of themultiplier circuit G2 is likewise determined on the basis of thecalculated Q. Also in this case, it is necessary that TP1 QT and thatTP2 Q-T

1. In a secondary radar reception system comprising: a primary radardevice including an antenna; a transmitter-receiver and a radarindicating device; a secondary radar receiver including an antennareceiving a response wave transmitted from a secondary radar in responseto a radar signal transmitted from the primary radar device; a receiverfor receiving the response wave received by the antenna and anidentification circuit consisting of at least two series connectedmultiple delay circuits; ''''and'''' circuits connected to the inputside of the first delay circuit and to the output side of the last delaycircuit and between each delay circuit and an ''''or'''' circuitconnected to the output side of the last delay circuit; asynchronization control circuit connected between the primary radardevice and the secondary radar receiver and supplying a first inputsignal to the ''''and'''' circuit connected to the output side of thelast delay circuit and to said ''''or'''' circuit and to said firstdelay circuit, the output of said ''''or'''' circuit connected to the''''and'''' circuit at the input of said first delay circuit, theresponse wave transmitted from the secondary radar being supplied tosaid ''''and'''' circuits at the inputs of said delay circuits, theoutput of the first stage delay circuit being supplied to a second inputterminal of the ''''and'''' circuit connected between the first andsecond delay circuits, the output of the last delay circuit beingsupplied to a first input terminal of the ''''and'''' circuit connectedto the output of said last delay circuit and to a first input terminalof said ''''or'''' circuit.
 2. A secondary radar reception system asclaimed in claim 1 in which the last delay circuit consists of N''scascaded delay elements, the output of an (N-n)th one of the delayelements and the response wave from the secondary radar being applied tothe ''''and'''' circuit connected to the output of the last delaycircuit where N and n are positive integers and N>n>0, thereby to obtainthe rise-up time of the response wave.
 3. A secondary radar receptionsystem as claimed in claim 1 in which said first delay circuit consistsof N''s delay elements, the output of an nth one of the delay elements(N>n>0 and N and n being positive integers) being connected to the firstinput terminal of the ''''and'''' circuit at the output of said firstdelay circuit, the response wave being applied to the other inputterminal of said ''''and'''' circuit and the output of said ''''and''''circuit being supplied to an (n + 1) th one of the delay elements.
 4. Asecondary radar reception system as claimed in claim 1 in which theresponse wave is supplied to a second input terminal of the ''''and''''circuit at the outputs of said delay circuits through a switchingcircuit and an ''''or'''' circuit.
 5. A secondary radar reception systemas claimed in claim 1 in which each of said delay circuits consists ofthree separate multiple delay circuits, the output terminal of a firstmultiple delay circuit being connected to a first input terminal of afirst ''''and'''' circuit, the response wave being fed to a second inputterminal of the first ''''and'''' circuit through a first switchingcircuit and a first ''''or'''' circuit, the output terminal of the first''''and'''' circuit being connected to the input terminal of the secondmultiple delay circuit, the output terminal of the second multiple delaycircuit being connected to the first input terminal of the second''''and'''' circuit, a rectangular wave output of the synchronizationcontrol circuit being supplied to the second input terminal of thesecond ''''and'''' circuit through a second switching circuit and asecond ''''or'''' circuit and the output terminal of the second''''and'''' circuit being connected to the third multiple delay circuit.6. A secondary radar reception system as claimed in claim 5 in which thefirst and second switching circuits are ganged together.